245 lines
12 KiB
Markdown
245 lines
12 KiB
Markdown
# cpuid
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### Intel CPUID library for Go Programming Language
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The cpuid package provides convenient and fast access to information from
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the x86 CPUID instruction.
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The package gathers all information during package initialization phase
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so its public interface will not need to execute the CPUID instruction at runtime.
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Frequent calls to the CPUID instruction can hurt performance,
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so this package makes it easier to do CPU-specific optimizations.
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[](https://godoc.org/github.com/intel-go/cpuid)
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### You can get it with
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```shell
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go get github.com/intel-go/cpuid
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```
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### Example:
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```go
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package main
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import (
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"github.com/intel-go/cpuid"
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"fmt"
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)
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func main() {
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fmt.Printf("VendorString: %s\n", cpuid.VendorIdentificatorString)
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fmt.Printf("Features: ")
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for i := uint64(0); i < 64; i++ {
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if cpuid.HasFeature(1 << i) {
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fmt.Printf("%s ", cpuid.FeatureNames[1<<i])
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}
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}
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fmt.Printf("\n")
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fmt.Printf("ExtendedFeatures: ")
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for i := uint64(0); i < 64; i++ {
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if cpuid.HasExtendedFeature(1 << i) {
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fmt.Printf("%s ", cpuid.ExtendedFeatureNames[1<<i])
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}
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}
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fmt.Printf("\n")
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fmt.Printf("ExtraFeatures: ")
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for i := uint64(0); i < 64; i++ {
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if cpuid.HasExtraFeature(1 << i) {
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fmt.Printf("%s ", cpuid.ExtraFeatureNames[1<<i])
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}
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}
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fmt.Printf("\n")
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}
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```
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### API description
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Most data is available with simple variables:
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* **SteppingId uint32** Processor Stepping ID
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* **ProcessorType uint32** Processor type
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* **DisplayFamily uint32** Processor family
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* **DisplayModel uint32** Processor model
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* **CacheLineSize uint32** Cache line size in bytes
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* **MaxLogocalCPUId uint32** Maximum number of addressable IDs for logical processors in this physical package
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* **InitialAPICId uint32** Initial APIC ID
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* **CacheDescriptors []CacheDescriptor** Cache descriptor's array
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You can iterate over them as follows:
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```go
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for _, cacheDescription := range cpuid.CacheDescriptors {
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fmt.Printf("CacheDescriptor: %v\n", cacheDescription)
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}
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```
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* **MonLineSizeMin uint32** Smallest monitor-line size in bytes (default is processor's monitor granularity)
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* **MonLineSizeMax uint32** Largest monitor-line size in bytes (default is processor's monitor granularity)
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* **MonitorEMX bool** Enumeration of Monitor-Mwait extensions availability status
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* **MonitorIBE bool** Supports treating interrupts as break-event for MWAIT flag
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* **EnabledAVX bool** EnabledAVX flag allows to check if feature AVX is enabled by OS/BIOS
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* **EnabledAVX512 bool** EnabledAVX512 flag allows to check if features AVX512xxx are enabled by OS/BIOS
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* **func HasFeature(feature uint64) bool** to check for the following features:
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> **SSE3** Prescott New Instructions-SSE3 (PNI) <br/>
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> **PCLMULQDQ** PCLMULQDQ support <br/>
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> **DTES64** 64-bit debug store (edx bit 21) <br/>
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> **MONITOR** MONITOR and MWAIT instructions (SSE3) <br/>
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> **DSI_CPL** CPL qualified debug store <br/>
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> **VMX** Virtual Machine eXtensions <br/>
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> **SMX** Safer Mode Extensions (LaGrande) <br/>
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> **EST** Enhanced SpeedStep <br/>
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> **TM2** Thermal Monitor 2 <br/>
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> **SSSE3** Supplemental SSE3 instructions <br/>
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> **CNXT_ID** L1 Context ID <br/>
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> **SDBG** Silicon Debug interface <br/>
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> **FMA** Fused multiply-add (FMA3) <br/>
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> **CX16** CMPXCHG16B instruction <br/>
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> **XTPR** Can disable sending task priority messages <br/>
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> **PDCM** Perfmon & debug capability <br/>
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> **PCID** Process context identifiers (CR4 bit 17) <br/>
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> **DCA** Direct cache access for DMA writes[10][11] <br/>
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> **SSE4_1** SSE4.1 instructions <br/>
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> **SSE4_2** SSE4.2 instructions <br/>
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> **X2APIC** x2APIC support <br/>
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> **MOVBE** MOVBE instruction (big-endian) <br/>
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> **POPCNT** POPCNT instruction <br/>
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> **TSC_DEADLINE** line APIC supports one-shot operation using a TSC deadline value <br/>
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> **AES** AES instruction set <br/>
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> **XSAVE** XSAVE, XRESTOR, XSETBV, XGETBV <BR/>
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> **OSXSAVE** XSAVE enabled by OS <br/>
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> **AVX** Advanced Vector Extensions <br/>
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> **F16C** F16C (half-precision) FP support <br/>
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> **RDRND** RDRAND (on-chip random number generator) support <br/>
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> **HYPERVISOR** Running on a hypervisor (always 0 on a real CPU, but also with some hypervisors) <br/>
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> **FPU** Onboard x87 FPU <br/>
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> **VME** Virtual 8086 mode extensions (such as VIF, VIP, PIV) <br/>
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> **DE** Debugging extensions (CR4 bit 3) <br/>
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> **PSE** Page Size Extension <br/>
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> **TSC** Time Stamp Counter <br/>
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> **MSR** Model-specific registers <br/>
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> **PAE** Physical Address Extension <br/>
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> **MCE** Machine Check Exception <br/>
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> **CX8** CMPXCHG8 (compare-and-swap) instruction <br/>
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> **APIC** Onboard Advanced Programmable Interrupt Controller <br/>
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> **SEP** SYSENTER and SYSEXIT instructions <br/>
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> **MTRR** Memory Type Range Registers <br/>
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> **PGE** Page Global Enable bit in CR4 <br/>
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> **MCA** Machine check architecture <br/>
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> **CMOV** Conditional move and FCMOV instructions <br/>
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> **PAT** Page Attribute Table <br/>
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> **PSE_36** 36-bit page size extension <br/>
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> **PSN** Processor Serial Number <br/>
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> **CLFSH** CLFLUSH instruction (SSE2) <br/>
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> **DS** Debug store: save trace of executed jumps <br/>
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> **ACPI** Onboard thermal control MSRs for ACPI <br/>
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> **MMX** MMX instructions <br/>
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> **FXSR** FXSAVE, FXRESTOR instructions, CR4 bit 9 <br/>
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> **SSE** SSE instructions (a.k.a. Katmai New Instructions) <br/>
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> **SSE2** SSE2 instructions <br/>
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> **SS** CPU cache supports self-snoop <br/>
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> **HTT** Hyper-threading <br/>
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> **TM** Thermal monitor automatically limits temperature <br/>
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> **IA64** IA64 processor emulating x86 <br/>
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> **PBE** Pending Break Enable (PBE# pin) wakeup support <br/>
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Usage example:
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```go
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if EnabledAVX && HasFeature(AVX) {
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fmt.Printf("We can use AVX\n")
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}
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```
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* **func HasExtendedFeature(feature uint64) bool** to check for the following features:
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> **FSGSBASE** Access to base of %fs and %gs<br/>
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> **IA32_TSC_ADJUST** IA32_TSC_ADJUST MSR is supported if 1<br/>
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> **BMI1** Bit Manipulation Instruction Set 1<br/>
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> **HLE** Transactional Synchronization Extensions<br/>
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> **AVX2** Advanced Vector Extensions 2<br/>
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> **SMEP** Supervisor-Mode Execution Prevention<br/>
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> **BMI2** Bit Manipulation Instruction Set 2<br/>
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> **ERMS** Enhanced REP MOVSB/STOSB<br/>
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> **INVPCID** INVPCID instruction<br/>
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> **RTM** Transactional Synchronization Extensions<br/>
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> **PQM** Supports Platform Quality of Service Monitoring (PQM) capability if 1<br/>
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> **DFPUCDS** Deprecates FPU CS and FPU DS values if 1<br/>
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> **MPX** Intel MPX (Memory Protection Extensions)<br/>
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> **PQE** Supports Platform Quality of Service Enforcement (PQE) capability if 1<br/>
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> **AVX512F** AVX-512 Foundation<br/>
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> **AVX512DQ** AVX-512 Doubleword and Quadword Instructions<br/>
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> **RDSEED** RDSEED instruction<br/>
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> **ADX** Intel ADX (Multi-Precision Add-Carry Instruction Extensions)<br/>
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> **SMAP** Supervisor Mode Access Prevention<br/>
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> **AVX512IFMA** AVX-512 Integer Fused Multiply-Add Instructions<br/>
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> **PCOMMIT** PCOMMIT instruction<br/>
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> **CLFLUSHOPT** CLFLUSHOPT instruction<br/>
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> **CLWB** CLWB instruction<br/>
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> **INTEL_PROCESSOR_TRACE** Intel Processor Trace<br/>
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> **AVX512PF** AVX-512 Prefetch Instructions<br/>
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> **AVX512ER** AVX-512 Exponential and Reciprocal Instructions<br/>
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> **AVX512CD** AVX-512 Conflict Detection Instructions<br/>
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> **SHA** Intel SHA extensions<br/>
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> **AVX512BW** AVX-512 Byte and Word Instructions<br/>
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> **AVX512VL** AVX-512 Vector Length Extensions<br/>
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> **PREFETCHWT1** PREFETCHWT1 instruction<br/>
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> **AVX512VBMI** AVX-512 Vector Bit Manipulation Instructions<br/>
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* **func HasExtraFeature(feature uint64) bool**
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> **LAHF_LM** LahfSahf LAHF and SAHF instruction support in 64-bit mod<br/>
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> **CMP_LEGACY** CmpLegacy Core multi-processing legacy mode.<br/>
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> **SVM** SVM Secure virtual machine.<br/>
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> **EXTAPIC** ExtApicSpace Extended APIC space.<br/>
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> **CR8_LEGACY** AltMovCr8 LOCK MOV CR0 means MOV CR8.<br/>
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> **ABM** ABM Advanced bit manipulation. LZCNT instruction support.<br/>
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> **SSE4A** SSE4A EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support.<br/>
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> **MISALIGNSSE** Misaligned SSE mode.<br/>
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> **PREFETCHW** PREFETCH and PREFETCHW instruction support.<br/>
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> **OSVW** OSVW OS visible workaround. Indicates OS-visible workaround support.<br/>
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> **IBS** IBS Instruction based sampling.<br/>
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> **XOP** XOP Extended operation support.<br/>
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> **SKINIT** SKINIT SKINIT and STGI are supported.<br/>
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> **WDT** WDT Watchdog timer support.<br/>
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> **LWP** LWP Lightweight profiling support.<br/>
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> **FMA4** FMA4 Four-operand FMA instruction support.<br/>
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> **TCE** Translation Cache Extension<br/>
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> **NODEID_MSR** NodeID MSR<br/>
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> **TBM** TBM Trailing bit manipulation instruction support.<br/>
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> **TOPOEXT** TopologyExtensio Topology extensions support.<br/>
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> **PERFCTR_CORE** PerfCtrExtCore Processor performance counter extensions support.<br/>
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> **PERFCTR_NB** PerfCtrExtNB NB performance counter extensions support.<br/>
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> **SPM** StreamPerfMon Streaming performance monitor architecture.<br/>
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> **DBX** DataBreakpointEx Data access breakpoint extension.<br/>
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> **PERFTSC** PerfTsc<br/>
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> **PCX_L2I** L2I perf counter extensions<br/>
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> **FPU_2** Onboard x87 FPU<br/>
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> **VME_2** Virtual mode extensions (VIF)<br/>
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> **DE_2** Debugging extensions (CR4 bit 3)<br/>
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> **PSE_2** Page Size Extension<br/>
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> **TSC_2** Time Stamp Counter<br/>
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> **MSR_2** Model-specific register<br/>
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> **PAE_2** Physical Address Extension<br/>
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> **MCE_2** Machine Check Exception<br/>
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> **CX8_2** CMPXCHG8 (compare-and-swap) instruction<br/>
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> **APIC_2** Onboard Advanced Programmable Interrupt Controller<br/>
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> **SYSCALL** SYSCALL and SYSRET instructions<br/>
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> **MTRR_2** Memory Type Range Registers<br/>
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> **PGE_2** Page Global Enable bit in CR4<br/>
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> **MCA_2** Machine check architecture<br/>
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> **CMOV_2** Conditional move and FCMOV instructions<br/>
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> **PAT_2** Page Attribute Table<br/>
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> **PSE36** 36-bit page size extension<br/>
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> **MP** Multiprocessor Capable<br/>
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> **NX** NX bit<br/>
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> **MMXEXT** Extended MMX<br/>
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> **MMX_2** MMX instructions<br/>
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> **FXSR_2** FXSAVE, FXRSTOR instructions<br/>
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> **FXSR_OPT** FXSAVE/FXRSTOR optimizations<br/>
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> **PDPE1GB** Gibibyte pages<br/>
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> **RDTSCP** RDTSCP instruction<br/>
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> **LM** Long mode<br/>
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> **_3DNOWEXT** Extended 3DNow!<br/>
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> **_3DNOW** 3DNow!<br/>
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