1123 lines
29 KiB
Go
1123 lines
29 KiB
Go
// Copyright 2015 Intel Corporation.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package cpuid provides access to inforamtion available with
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// CPUID instruction
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// All information is gathered during package initialization phase
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// so package's public interface doesn't call CPUID intstruction
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package cpuid
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// VendorIndentificationString like "GenuineIntel" or "AuthenticAMD"
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var VendorIdentificatorString string
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// ProcessorBrandString like "Intel(R) Core(TM) i7-4770HQ CPU @ 2.20GHz"
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var ProcessorBrandString string
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// SteppingId is Processor Stepping ID as described in
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// Intel® 64 and IA-32 Architectures Software Developer’s Manual
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var SteppingId uint32
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// ProcessorType obtained from processor Version Information, according to
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// Intel® 64 and IA-32 Architectures Software Developer’s Manual
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var ProcessorType uint32
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// DisplayFamily is Family of processors obtained from processor Version Information, according to
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// Intel® 64 and IA-32 Architectures Software Developer’s Manual
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var DisplayFamily uint32
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// Display Model is Model of processor obtained from processor Version Information, according to
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// Intel® 64 and IA-32 Architectures Software Developer’s Manual
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var DisplayModel uint32
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// Cache line size in bytes
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var CacheLineSize uint32
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// Maximum number of addressable IDs for logical processors in this physical package
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var MaxLogocalCPUId uint32
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// Initial APIC ID
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var InitialAPICId uint32
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// Cache descriptor's array
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// You can iterate like there:
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// for _, cacheDescription := range cpuid.CacheDescriptors {
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// fmt.Printf("CacheDescriptor: %v\n", cacheDescription)
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// }
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// See CacheDescriptor type for more information
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var CacheDescriptors []CacheDescriptor
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// Smallest monitor-line size in bytes (default is processor's monitor granularity)
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var MonLineSizeMin uint32
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// Largest monitor-line size in bytes (default is processor's monitor granularity)
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var MonLineSizeMax uint32
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// Enumeration of Monitor-Mwait extensions availability status
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var MonitorEMX bool
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// Supports treating interrupts as break-event for MWAIT flag
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var MonitorIBE bool
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// EnabledAVX flag allows to check if feature AVX is enabled by OS/BIOS
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var EnabledAVX bool = false
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// EnabledAVX512 flag allows to check if features AVX512xxx are enabled by OS/BIOS
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var EnabledAVX512 bool = false
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type CacheDescriptor struct {
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Level int // Cache level
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CacheType int // Cache type
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CacheName string // Name
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CacheSize int // in KBytes (of page size for TLB)
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Ways int // Associativity, 0 undefined, 0xFF fully associate
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LineSize int // Cache line size in bytes
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Entries int // number of entries for TLB
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Partioning int // partitioning
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}
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// ThermalSensorInterruptThresholds is the number of interrupt thresholds in digital thermal sensor.
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var ThermalSensorInterruptThresholds uint32
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// HasFeature to check if features from FeatureNames map are available on the current processor
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func HasFeature(feature uint64) bool {
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return (featureFlags & feature) != 0
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}
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// HasExtendedFeature to check if features from ExtendedFeatureNames map are available on the current processor
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func HasExtendedFeature(feature uint64) bool {
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return (extendedFeatureFlags & feature) != 0
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}
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// HasExtraFeature to check if features from ExtraFeatureNames map are available on the current processor
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func HasExtraFeature(feature uint64) bool {
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return (extraFeatureFlags & feature) != 0
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}
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// HasThermalAndPowerFeature to check if features from ThermalAndPowerFeatureNames map are available on the current processor
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func HasThermalAndPowerFeature(feature uint32) bool {
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return (thermalAndPowerFeatureFlags & feature) != 0
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}
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var FeatureNames = map[uint64]string{
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SSE3: "SSE3",
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PCLMULQDQ: "PCLMULQDQ",
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DTES64: "DTES64",
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MONITOR: "MONITOR",
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DSI_CPL: "DSI_CPL",
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VMX: "VMX",
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SMX: "SMX",
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EST: "EST",
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TM2: "TM2",
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SSSE3: "SSSE3",
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CNXT_ID: "CNXT_ID",
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SDBG: "SDBG",
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FMA: "FMA",
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CX16: "CX16",
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XTPR: "XTPR",
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PDCM: "PDCM",
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PCID: "PCID",
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DCA: "DCA",
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SSE4_1: "SSE4_1",
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SSE4_2: "SSE4_2",
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X2APIC: "X2APIC",
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MOVBE: "MOVBE",
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POPCNT: "POPCNT",
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TSC_DEADLINE: "TSC_DEADLINE",
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AES: "AES",
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XSAVE: "XSAVE",
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OSXSAVE: "OSXSAVE",
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AVX: "AVX",
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F16C: "F16C",
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RDRND: "RDRND",
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HYPERVISOR: "HYPERVISOR",
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FPU: "FPU",
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VME: "VME",
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DE: "DE",
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PSE: "PSE",
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TSC: "TSC",
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MSR: "MSR",
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PAE: "PAE",
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MCE: "MCE",
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CX8: "CX8",
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APIC: "APIC",
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SEP: "SEP",
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MTRR: "MTRR",
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PGE: "PGE",
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MCA: "MCA",
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CMOV: "CMOV",
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PAT: "PAT",
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PSE_36: "PSE_36",
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PSN: "PSN",
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CLFSH: "CLFSH",
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DS: "DS",
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ACPI: "ACPI",
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MMX: "MMX",
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FXSR: "FXSR",
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SSE: "SSE",
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SSE2: "SSE2",
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SS: "SS",
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HTT: "HTT",
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TM: "TM",
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IA64: "IA64",
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PBE: "PBE",
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}
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var ThermalAndPowerFeatureNames = map[uint32]string{ // From leaf06
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ARAT: "ARAT",
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PLN: "PLN",
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ECMD: "ECMD",
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PTM: "PTM",
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HDC: "HDC",
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HCFC: "HCFC",
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HWP: "HWP",
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HWP_NOTIF: "HWP_NOTIF",
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HWP_ACTIVITY_WINDOW: "HWP_ACTIVITY_WINDOW",
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HWP_ENERGY_PERFORMANCE: "HWP_ENERGY_PERFORMANCE",
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HWP_PACKAGE_LEVEL_REQUEST: "HWP_PACKAGE_LEVEL_REQUEST",
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PERFORMANCE_ENERGY_BIAS: "PERFORMANCE_ENERGY_BIAS",
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TEMPERATURE_SENSOR: "TEMPERATURE_SENSOR",
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TURBO_BOOST: "TURBO_BOOST",
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TURBO_BOOST_MAX: "TURBO_BOOST_MAX",
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}
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var ExtendedFeatureNames = map[uint64]string{ // From leaf07
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FSGSBASE: "FSGSBASE",
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IA32_TSC_ADJUST: "IA32_TSC_ADJUST",
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BMI1: "BMI1",
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HLE: "HLE",
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AVX2: "AVX2",
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SMEP: "SMEP",
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BMI2: "BMI2",
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ERMS: "ERMS",
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INVPCID: "INVPCID",
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RTM: "RTM",
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PQM: "PQM",
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DFPUCDS: "DFPUCDS",
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MPX: "MPX",
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PQE: "PQE",
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AVX512F: "AVX512F",
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AVX512DQ: "AVX512DQ",
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RDSEED: "RDSEED",
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ADX: "ADX",
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SMAP: "SMAP",
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AVX512IFMA: "AVX512IFMA",
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PCOMMIT: "PCOMMIT",
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CLFLUSHOPT: "CLFLUSHOPT",
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CLWB: "CLWB",
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INTEL_PROCESSOR_TRACE: "INTEL_PROCESSOR_TRACE",
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AVX512PF: "AVX512PF",
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AVX512ER: "AVX512ER",
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AVX512CD: "AVX512CD",
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SHA: "SHA",
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AVX512BW: "AVX512BW",
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AVX512VL: "AVX512VL",
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PREFETCHWT1: "PREFETCHWT1",
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AVX512VBMI: "AVX512VBMI",
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}
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var ExtraFeatureNames = map[uint64]string{ // From leaf 8000 0001
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LAHF_LM: "LAHF_LM",
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CMP_LEGACY: "CMP_LEGACY",
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SVM: "SVM",
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EXTAPIC: "EXTAPIC",
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CR8_LEGACY: "CR8_LEGACY",
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ABM: "ABM",
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SSE4A: "SSE4A",
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MISALIGNSSE: "MISALIGNSSE",
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PREFETCHW: "PREFETCHW",
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OSVW: "OSVW",
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IBS: "IBS",
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XOP: "XOP",
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SKINIT: "SKINIT",
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WDT: "WDT",
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LWP: "LWP",
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FMA4: "FMA4",
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TCE: "TCE",
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NODEID_MSR: "NODEID_MSR",
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TBM: "TBM",
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TOPOEXT: "TOPOEXT",
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PERFCTR_CORE: "PERFCTR_CORE",
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PERFCTR_NB: "PERFCTR_NB",
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SPM: "SPM",
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DBX: "DBX",
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PERFTSC: "PERFTSC",
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PCX_L2I: "PCX_L2I",
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FPU_2: "FPU",
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VME_2: "VME",
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DE_2: "DE",
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PSE_2: "PSE",
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TSC_2: "TSC",
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MSR_2: "MSR",
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PAE_2: "PAE",
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MCE_2: "MCE",
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CX8_2: "CX8",
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APIC_2: "APIC",
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SYSCALL: "SYSCALL",
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MTRR_2: "MTRR",
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PGE_2: "PGE",
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MCA_2: "MCA",
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CMOV_2: "CMOV",
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PAT_2: "PAT",
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PSE36: "PSE36",
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MP: "MP",
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NX: "NX",
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MMXEXT: "MMXEXT",
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MMX_2: "MMX",
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FXSR_2: "FXSR",
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FXSR_OPT: "FXSR_OPT",
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PDPE1GB: "PDPE1GB",
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RDTSCP: "RDTSCP",
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LM: "LM",
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_3DNOWEXT: "3DNOWEXT",
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_3DNOW: "3DNOW",
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}
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var brandStrings = map[string]int{
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"AMDisbetter!": AMD,
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"AuthenticAMD": AMD,
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"CentaurHauls": CENTAUR,
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"CyrixInstead": CYRIX,
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"GenuineIntel": INTEL,
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"TransmetaCPU": TRANSMETA,
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"GenuineTMx86": TRANSMETA,
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"Geode by NSC": NATIONALSEMICONDUCTOR,
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"NexGenDriven": NEXGEN,
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"RiseRiseRise": RISE,
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"SiS SiS SiS ": SIS,
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"UMC UMC UMC ": UMC,
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"VIA VIA VIA ": VIA,
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"Vortex86 SoC": VORTEX,
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"KVMKVMKVM": KVM,
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"Microsoft Hv": HYPERV,
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"VMwareVMware": VMWARE,
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"XenVMMXenVMM": XEN,
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}
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var maxInputValue uint32
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var maxExtendedInputValue uint32
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var extendedModelId uint32
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var extendedFamilyId uint32
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var brandIndex uint32
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var brandId int
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var featureFlags uint64
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var thermalAndPowerFeatureFlags uint32
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var extendedFeatureFlags uint64
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var extraFeatureFlags uint64
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func cpuid_low(arg1, arg2 uint32) (eax, ebx, ecx, edx uint32) // implemented in cpuidlow_amd64.s
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func xgetbv_low(arg1 uint32) (eax, edx uint32) // implemented in cpuidlow_amd64.s
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func init() {
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detectFeatures()
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}
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const (
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UKNOWN = iota
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AMD
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CENTAUR
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CYRIX
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INTEL
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TRANSMETA
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NATIONALSEMICONDUCTOR
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NEXGEN
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RISE
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SIS
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UMC
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VIA
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VORTEX
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KVM
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HYPERV
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VMWARE
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XEN
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)
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func detectFeatures() {
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leaf0()
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leaf1()
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leaf2()
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leaf3()
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leaf4()
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leaf5()
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leaf6()
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leaf7()
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leaf0x80000000()
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leaf0x80000001()
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leaf0x80000004()
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leaf0x80000005()
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leaf0x80000006()
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if HasFeature(OSXSAVE) {
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eax, _ := xgetbv_low(0)
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if (eax & 0x6) == 0x6 {
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EnabledAVX = true
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}
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if (eax & 0xE0) == 0xE0 {
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EnabledAVX512 = true
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}
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}
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}
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const (
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SSE3 = uint64(1) << iota
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PCLMULQDQ
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DTES64
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MONITOR
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DSI_CPL
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VMX
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SMX
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EST
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TM2
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SSSE3
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CNXT_ID
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SDBG
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FMA
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CX16
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XTPR
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PDCM
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_
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PCID
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DCA
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SSE4_1
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SSE4_2
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X2APIC
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MOVBE
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POPCNT
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TSC_DEADLINE
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AES
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XSAVE
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OSXSAVE
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AVX
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F16C
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RDRND
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HYPERVISOR
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FPU
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VME
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DE
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PSE
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TSC
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MSR
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PAE
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MCE
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CX8
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APIC
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_
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SEP
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MTRR
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PGE
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MCA
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CMOV
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PAT
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PSE_36
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PSN
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CLFSH
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_
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DS
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ACPI
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MMX
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FXSR
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SSE
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SSE2
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SS
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HTT
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TM
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IA64
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PBE
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)
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const (
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FSGSBASE = uint64(1) << iota
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IA32_TSC_ADJUST
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_
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BMI1
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HLE
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AVX2
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_
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SMEP
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BMI2
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ERMS
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INVPCID
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RTM
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PQM
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DFPUCDS
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MPX
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PQE
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AVX512F
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AVX512DQ
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RDSEED
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ADX
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SMAP
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AVX512IFMA
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PCOMMIT
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CLFLUSHOPT
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CLWB
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INTEL_PROCESSOR_TRACE
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AVX512PF
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AVX512ER
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AVX512CD
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SHA
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AVX512BW
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AVX512VL
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// ECX's const from there
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PREFETCHWT1
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AVX512VBMI
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)
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const (
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LAHF_LM = uint64(1) << iota
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CMP_LEGACY
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SVM
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EXTAPIC
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CR8_LEGACY
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ABM
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SSE4A
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MISALIGNSSE
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PREFETCHW
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OSVW
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||
IBS
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XOP
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SKINIT
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WDT
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_
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LWP
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FMA4
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TCE
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||
_
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NODEID_MSR
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_
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TBM
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TOPOEXT
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PERFCTR_CORE
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PERFCTR_NB
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SPM
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DBX
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PERFTSC
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||
PCX_L2I
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||
_
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||
_
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||
_
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||
// EDX features from there
|
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FPU_2
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VME_2
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||
DE_2
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PSE_2
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TSC_2
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||
MSR_2
|
||
PAE_2
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MCE_2
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CX8_2
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APIC_2
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_
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SYSCALL
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MTRR_2
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PGE_2
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MCA_2
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CMOV_2
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PAT_2
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||
PSE36
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_
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MP
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NX
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||
_
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MMXEXT
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||
MMX_2
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||
FXSR_2
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||
FXSR_OPT
|
||
PDPE1GB
|
||
RDTSCP
|
||
_
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||
LM
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_3DNOWEXT
|
||
_3DNOW
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||
)
|
||
|
||
// Thermal and Power Management features
|
||
const (
|
||
// EAX bits 0-15
|
||
TEMPERATURE_SENSOR = uint32(1) << iota // Digital temperature sensor
|
||
TURBO_BOOST // Intel Turbo Boost Technology available
|
||
ARAT // APIC-Timer-always-running feature is supported if set.
|
||
_ // Reserved
|
||
PLN // Power limit notification controls
|
||
ECMD // Clock modulation duty cycle extension
|
||
PTM // Package thermal management
|
||
HWP // HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS)
|
||
HWP_NOTIF // IA32_HWP_INTERRUPT MSR
|
||
HWP_ACTIVITY_WINDOW // IA32_HWP_REQUEST[bits 41:32]
|
||
HWP_ENERGY_PERFORMANCE // IA32_HWP_REQUEST[bits 31:24]
|
||
HWP_PACKAGE_LEVEL_REQUEST // IA32_HWP_REQUEST_PKG MSR
|
||
_ // Reserved (eax bit 12)
|
||
HDC // HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs
|
||
TURBO_BOOST_MAX // Intel® Turbo Boost Max Technology
|
||
_ // Reserved (eax bit 15)
|
||
|
||
// ECX bits 0-15
|
||
HCFC // Hardware Coordination Feedback Capability
|
||
_
|
||
_
|
||
PERFORMANCE_ENERGY_BIAS // Processor supports performance-energy bias preference
|
||
)
|
||
|
||
const (
|
||
NULL = iota
|
||
DATA_CACHE
|
||
INSTRUCTION_CACHE
|
||
UNIFIED_CACHE
|
||
TLB
|
||
DTLB
|
||
STLB
|
||
PREFETCH
|
||
)
|
||
|
||
var leaf02Names = [...]string{
|
||
"NULL",
|
||
"DATA_CACHE",
|
||
"INSTRUCTION_CACHE",
|
||
"UNIFIED_CACHE",
|
||
"TLB",
|
||
"DTLB",
|
||
"STLB",
|
||
"PREFETCH",
|
||
}
|
||
|
||
func leaf0() {
|
||
|
||
eax, ebx, ecx, edx := cpuid_low(0, 0)
|
||
|
||
maxInputValue = eax
|
||
|
||
VendorIdentificatorString = string(int32sToBytes(ebx, edx, ecx))
|
||
brandId = brandStrings[VendorIdentificatorString]
|
||
}
|
||
|
||
func leaf1() {
|
||
|
||
if maxInputValue < 1 {
|
||
return
|
||
}
|
||
|
||
eax, ebx, ecx, edx := cpuid_low(1, 0)
|
||
// Parse EAX
|
||
SteppingId = (eax & 0xF)
|
||
modelId := (eax >> 4) & 0xF
|
||
familyId := (eax >> 8) & 0xF
|
||
ProcessorType = (eax >> 12) & 0x3
|
||
ExtendedModelId := (eax >> 16) & 0xF
|
||
extendedFamilyId := (eax >> 20) & 0xFF
|
||
|
||
DisplayFamily = familyId
|
||
DisplayModel = modelId
|
||
|
||
if familyId == 0xF {
|
||
DisplayFamily = extendedFamilyId + familyId
|
||
}
|
||
|
||
if familyId == 0x6 || familyId == 0xF {
|
||
DisplayModel = ExtendedModelId<<4 + modelId
|
||
}
|
||
|
||
// Parse EBX
|
||
brandIndex = ebx & 0xFF
|
||
CacheLineSize = ((ebx >> 8) & 0xFF) << 3
|
||
MaxLogocalCPUId = (ebx >> 16) & 0xFF
|
||
InitialAPICId = (ebx >> 24)
|
||
|
||
// Parse ECX & EDX not needed. Ask through HasFeature function
|
||
featureFlags = (uint64(edx) << 32) | uint64(ecx)
|
||
}
|
||
|
||
func leaf2() {
|
||
|
||
if brandId != INTEL {
|
||
return
|
||
}
|
||
if maxInputValue < 2 {
|
||
return
|
||
}
|
||
|
||
bytes := int32sToBytes(cpuid_low(2, 0))
|
||
|
||
for i := 0; i < len(bytes); i++ {
|
||
if (i%4 == 0) && (bytes[i+3]&(1<<7) != 0) {
|
||
i += 4
|
||
continue
|
||
}
|
||
if bytes[i] == 0xFF { // it means that we should use leaf 4 for cache info
|
||
CacheDescriptors = CacheDescriptors[0:0]
|
||
break
|
||
}
|
||
CacheDescriptors = append(CacheDescriptors, leaf02Descriptors[int16(bytes[i])])
|
||
}
|
||
}
|
||
|
||
func leaf3() {
|
||
if brandId != INTEL {
|
||
return
|
||
}
|
||
|
||
if maxInputValue < 3 {
|
||
return
|
||
}
|
||
// TODO SerialNumber for < Pentium 4
|
||
}
|
||
|
||
func leaf4() {
|
||
|
||
if brandId != INTEL {
|
||
return
|
||
}
|
||
|
||
if maxInputValue < 4 {
|
||
return
|
||
}
|
||
|
||
cacheId := 0
|
||
for {
|
||
eax, ebx, ecx, _ := cpuid_low(4, uint32(cacheId))
|
||
cacheId++
|
||
cacheType := eax & 0xF
|
||
|
||
if cacheType == NULL {
|
||
break
|
||
}
|
||
|
||
cacheLevel := (eax >> 5) & 0x7
|
||
// selfInitializingCacheLevel := eax & (1<<8)
|
||
// fullyAssociativeCache := eax & (1<<9)
|
||
// maxNumLogicalCoresSharing := (eax >> 14) & 0x3FF
|
||
// maxNumPhisCores := (eax >> 26) & 0x3F
|
||
systemCoherencyLineSize := (ebx & 0xFFF) + 1
|
||
physicalLinePartions := (ebx>>12)&0x3FF + 1
|
||
waysOfAssiociativity := (ebx>>22)&0x3FF + 1
|
||
numberOfSets := ecx + 1
|
||
// writeBackInvalidate := edx & 1
|
||
// cacheInclusiveness := edx & (1<<1)
|
||
// complexCacheIndexing := edx & (1<<2)
|
||
cacheSize := (waysOfAssiociativity * physicalLinePartions *
|
||
systemCoherencyLineSize * numberOfSets) >> 10
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{int(cacheLevel),
|
||
int(cacheType),
|
||
"",
|
||
int(cacheSize),
|
||
int(waysOfAssiociativity),
|
||
int(systemCoherencyLineSize),
|
||
int(numberOfSets),
|
||
int(physicalLinePartions),
|
||
})
|
||
}
|
||
}
|
||
|
||
func leaf5() {
|
||
if maxInputValue < 5 {
|
||
return
|
||
}
|
||
|
||
eax, ebx, ecx, _ := cpuid_low(4, 0) // TODO process EDX with C0-C7 C-states
|
||
MonLineSizeMax = eax & (0xFFFF)
|
||
MonLineSizeMax = ebx & (0xFFFF)
|
||
MonitorEMX = (ecx & (1 << 0)) != 0
|
||
MonitorIBE = (ecx & (1 << 1)) != 0
|
||
|
||
}
|
||
|
||
func leaf6() {
|
||
// Thermal and Power Management Features for Intel
|
||
if maxInputValue < 6 {
|
||
return
|
||
}
|
||
|
||
eax, ebx, ecx, _ := cpuid_low(6, 0)
|
||
thermalAndPowerFeatureFlags = (eax & 0xFFFF) | (ecx << 16)
|
||
ThermalSensorInterruptThresholds = ebx & 7
|
||
}
|
||
|
||
func leaf7() {
|
||
_, ebx, ecx, _ := cpuid_low(7, 0)
|
||
extendedFeatureFlags = (uint64(ecx) << 32) | uint64(ebx)
|
||
}
|
||
|
||
func leaf0x80000000() {
|
||
maxExtendedInputValue, _, _, _ = cpuid_low(0x80000000, 0)
|
||
}
|
||
|
||
func leaf0x80000001() {
|
||
if maxExtendedInputValue < 0x80000001 {
|
||
return
|
||
}
|
||
_, _, ecx, edx := cpuid_low(0x80000001, 0)
|
||
//extendedProcessorSignatureAndFeatureBits := eax
|
||
extraFeatureFlags = (uint64(edx) << 32) | uint64(ecx)
|
||
}
|
||
|
||
// leaf0x80000004 looks at the Processor Brand String in leaves 0x80000002 through 0x80000004
|
||
func leaf0x80000004() {
|
||
if maxExtendedInputValue < 0x80000004 {
|
||
return
|
||
}
|
||
|
||
ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000002, 0)))
|
||
ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000003, 0)))
|
||
ProcessorBrandString += string(int32sToBytes(cpuid_low(0x80000004, 0)))
|
||
}
|
||
|
||
func leaf0x80000005() {
|
||
// AMD L1 Cache and TLB Information
|
||
if maxExtendedInputValue < 0x80000005 {
|
||
return
|
||
}
|
||
|
||
if brandId != AMD {
|
||
return
|
||
}
|
||
|
||
eax, ebx, ecx, edx := cpuid_low(0x80000005, 0)
|
||
|
||
L1DTlb2and4MAssoc := (eax >> 24) & 0xFF
|
||
L1DTlb2and4MSize := (eax >> 16) & 0xFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
DTLB,
|
||
"DTLB 2M/4M",
|
||
2 * 1024,
|
||
int(L1DTlb2and4MAssoc),
|
||
-1,
|
||
int(L1DTlb2and4MSize),
|
||
0,
|
||
})
|
||
|
||
L1ITlb2and4MAssoc := (eax >> 8) & 0xFF
|
||
L1ITlb2and4MSize := (eax) & 0xFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
TLB,
|
||
"ITLB 2M/4M",
|
||
2 * 1024,
|
||
int(L1ITlb2and4MAssoc),
|
||
-1,
|
||
int(L1ITlb2and4MSize),
|
||
0,
|
||
})
|
||
|
||
L1DTlb4KAssoc := (ebx >> 24) & 0xFF
|
||
L1DTlb4KSize := (ebx >> 16) & 0xFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
DTLB,
|
||
"DTLB 4K",
|
||
4,
|
||
int(L1DTlb4KAssoc),
|
||
-1,
|
||
int(L1DTlb4KSize),
|
||
0,
|
||
})
|
||
|
||
L1ITlb4KAssoc := (ebx >> 8) & 0xFF
|
||
L1ITlb4KSize := (ebx) & 0xFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
TLB,
|
||
"ITLB 4K",
|
||
4,
|
||
int(L1ITlb4KAssoc),
|
||
-1,
|
||
int(L1ITlb4KSize),
|
||
0,
|
||
})
|
||
|
||
L1DcSize := (ecx >> 24) & 0xFF
|
||
L1DcAssoc := (ecx >> 16) & 0xFF
|
||
L1DcLinesPerTag := (ecx >> 8) & 0xFF
|
||
L1DcLineSize := (ecx >> 0) & 0xFF
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
DATA_CACHE,
|
||
"L1 Data cache",
|
||
int(L1DcSize),
|
||
int(L1DcAssoc),
|
||
int(L1DcLineSize),
|
||
-1,
|
||
int(L1DcLinesPerTag),
|
||
})
|
||
|
||
L1IcSize := (edx >> 24) & 0xFF
|
||
L1IcAssoc := (edx >> 16) & 0xFF
|
||
L1IcLinesPerTag := (edx >> 8) & 0xFF
|
||
L1IcLineSize := (edx >> 0) & 0xFF
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{1,
|
||
INSTRUCTION_CACHE,
|
||
"L1 Instruction cache",
|
||
int(L1IcSize),
|
||
int(L1IcAssoc),
|
||
int(L1IcLineSize),
|
||
-1,
|
||
int(L1IcLinesPerTag),
|
||
})
|
||
}
|
||
|
||
func leaf0x80000006() {
|
||
|
||
if maxExtendedInputValue < 0x80000006 {
|
||
return
|
||
}
|
||
|
||
var associativityEncodings = map[uint]uint{
|
||
0x00: 0,
|
||
0x01: 1,
|
||
0x02: 2,
|
||
0x04: 4,
|
||
0x06: 8,
|
||
0x08: 16,
|
||
0x0A: 32,
|
||
0x0B: 48,
|
||
0x0C: 64,
|
||
0x0D: 96,
|
||
0x0E: 128,
|
||
0x0F: 0xFF, // - Fully associative
|
||
}
|
||
|
||
eax, ebx, ecx, edx := cpuid_low(0x80000006, 0)
|
||
|
||
if brandId == INTEL {
|
||
|
||
CacheLineSize := (ecx >> 0) & 0xFF
|
||
L2Associativity := uint((ecx >> 12) & 0xF)
|
||
CacheSize := (ecx >> 16) & 0xFFFF
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
0,
|
||
"Cache info from leaf 0x80000006 for Intel",
|
||
int(CacheSize),
|
||
int(associativityEncodings[L2Associativity]),
|
||
int(CacheLineSize),
|
||
-1,
|
||
0,
|
||
})
|
||
}
|
||
|
||
if brandId == AMD {
|
||
|
||
L2DTlb2and4MAssoc := uint((eax >> 28) & 0xF)
|
||
L2DTlb2and4MSize := (eax >> 16) & 0xFFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
DTLB,
|
||
"DTLB 2M/4M",
|
||
2 * 1024,
|
||
int(associativityEncodings[L2DTlb2and4MAssoc]),
|
||
-1,
|
||
int(L2DTlb2and4MSize),
|
||
0,
|
||
})
|
||
|
||
L2ITlb2and4MAssoc := uint((eax >> 12) & 0xF)
|
||
L2ITlb2and4MSize := (eax) & 0xFFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
TLB,
|
||
"ITLB 2M/4M",
|
||
2 * 1024,
|
||
int(associativityEncodings[L2ITlb2and4MAssoc]),
|
||
-1,
|
||
int(L2ITlb2and4MSize),
|
||
0,
|
||
})
|
||
|
||
L2DTlb4KAssoc := uint((ebx >> 28) & 0xF)
|
||
L2DTlb4KSize := (ebx >> 16) & 0xFFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
DTLB,
|
||
"DTLB 4K",
|
||
4,
|
||
int(associativityEncodings[L2DTlb4KAssoc]),
|
||
-1,
|
||
int(L2DTlb4KSize),
|
||
0,
|
||
})
|
||
|
||
L2ITlb4KAssoc := uint((ebx >> 12) & 0xF)
|
||
L2ITlb4KSize := (ebx) & 0xFFF
|
||
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
TLB,
|
||
"ITLB 4K",
|
||
4,
|
||
int(associativityEncodings[L2ITlb4KAssoc]),
|
||
-1,
|
||
int(L2ITlb4KSize),
|
||
0,
|
||
})
|
||
|
||
L2Size := (ecx >> 16) & 0xFFFF
|
||
L2Assoc := uint((ecx >> 12) & 0xF)
|
||
L2LinesPerTag := (ecx >> 8) & 0xF
|
||
L2LineSize := (ecx >> 0) & 0xFF
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{2,
|
||
DATA_CACHE,
|
||
"L2 Data cache",
|
||
int(L2Size),
|
||
int(associativityEncodings[L2Assoc]),
|
||
int(L2LineSize),
|
||
-1,
|
||
int(L2LinesPerTag),
|
||
})
|
||
|
||
L3Size := ((edx >> 18) & 0xF) * 512
|
||
L3Assoc := uint((edx >> 12) & 0xF)
|
||
L3LinesPerTag := (edx >> 8) & 0xF
|
||
L3LineSize := (edx >> 0) & 0xFF
|
||
CacheDescriptors = append(CacheDescriptors,
|
||
CacheDescriptor{3,
|
||
DATA_CACHE,
|
||
"L3 Data cache",
|
||
int(L3Size),
|
||
int(associativityEncodings[L3Assoc]),
|
||
int(L3LineSize),
|
||
-1,
|
||
int(L3LinesPerTag),
|
||
})
|
||
}
|
||
}
|
||
|
||
// TODO split fused descritops with bits in high key's byte like for 0x49
|
||
var leaf02Descriptors = map[int16]CacheDescriptor{
|
||
0x01: {-1, TLB, "Instruction TLB", 4, 4, -1, 32, 0},
|
||
0x02: {-1, TLB, "Instruction TLB", 4 * 1024, 0xFF, -1, 2, 0},
|
||
0x03: {-1, TLB, "Data TLB", 4, 4, -1, 64, 0},
|
||
0x04: {-1, TLB, "Data TLB", 4 * 1024, 4, -1, 8, 0},
|
||
0x05: {-1, TLB, "Data TLB1", 4 * 1024, 4, -1, 32, 0},
|
||
0x06: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 8, 4, 32, -1, 0},
|
||
0x08: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 16, 4, 32, -1, 0},
|
||
0x09: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 32, 4, 64, -1, 0},
|
||
0x0A: {1, DATA_CACHE, "1st-level data cache", 8, 2, 32, -1, 0},
|
||
0x0B: {-1, TLB, "Instruction TLB", 4 * 1024, 4, -1, 4, 0},
|
||
0x0C: {1, DATA_CACHE, "1st-level data cache", 16, 4, 32, -1, 0},
|
||
0x0D: {1, DATA_CACHE, "1st-level data cache", 16, 4, 64, -1, 0},
|
||
0x0E: {1, DATA_CACHE, "1st-level data cache", 24, 6, 64, -1, 0},
|
||
0x1D: {2, DATA_CACHE, "2nd-level cache", 128, 2, 64, -1, 0},
|
||
0x21: {2, DATA_CACHE, "2nd-level cache", 256, 8, 64, -1, 0},
|
||
0x22: {3, DATA_CACHE, "3nd-level cache", 512, 4, 64, -1, 2},
|
||
0x23: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 8, 64, -1, 2},
|
||
0x24: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 16, 64, -1, 0},
|
||
0x25: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 8, 64, -1, 2},
|
||
0x29: {3, DATA_CACHE, "2nd-level cache", 4 * 1024, 8, 64, -1, 2},
|
||
0x2C: {1, DATA_CACHE, "1st-level cache", 32, 8, 64, -1, 0},
|
||
0x30: {1, INSTRUCTION_CACHE, "1st-level instruction cache", 32, 8, 64, -1, 0},
|
||
0x40: {-1, DATA_CACHE, "No 2nd-level cache or, if processor contains a " +
|
||
"valid 2nd-level cache, no 3rd-level cache", -1, -1, -1, -1, 0},
|
||
0x41: {2, DATA_CACHE, "2nd-level cache", 128, 4, 32, -1, 0},
|
||
0x42: {2, DATA_CACHE, "2nd-level cache", 256, 4, 32, -1, 0},
|
||
0x43: {2, DATA_CACHE, "2nd-level cache", 512, 4, 32, -1, 0},
|
||
0x44: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 4, 32, -1, 0},
|
||
0x45: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 4, 32, -1, 0},
|
||
0x46: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 4, 64, -1, 0},
|
||
0x47: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 8, 64, -1, 0},
|
||
0x48: {2, DATA_CACHE, "2nd-level cache", 3 * 1024, 12, 64, -1, 0},
|
||
0x49: {2, DATA_CACHE, "2nd-level cache", 4 * 1024, 16, 64, -1, 0},
|
||
// (Intel Xeon processor MP, Family 0FH, Model 06H)
|
||
(0x49 | (1 << 8)): {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 16, 64, -1, 0},
|
||
0x4A: {3, DATA_CACHE, "3nd-level cache", 6 * 1024, 12, 64, -1, 0},
|
||
0x4B: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 16, 64, -1, 0},
|
||
0x4C: {3, DATA_CACHE, "3nd-level cache", 12 * 1024, 12, 64, -1, 0},
|
||
0x4D: {3, DATA_CACHE, "3nd-level cache", 16 * 1024, 16, 64, -1, 0},
|
||
0x4E: {2, DATA_CACHE, "3nd-level cache", 6 * 1024, 24, 64, -1, 0},
|
||
0x4F: {-1, TLB, "Instruction TLB", 4, -1, -1, 32, 0},
|
||
0x50: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 64, 0},
|
||
0x51: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 128, 0},
|
||
0x52: {-1, TLB, "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages", 4, -1, -1, 256, 0},
|
||
0x55: {-1, TLB, "Instruction TLB: 2-MByte or 4-MByte pages", 2 * 1024, 0xFF, -1, 7, 0},
|
||
0x56: {-1, TLB, "Data TLB0", 4 * 1024, 4, -1, 16, 0},
|
||
0x57: {-1, TLB, "Data TLB0", 4, 4, -1, 16, 0},
|
||
0x59: {-1, TLB, "Data TLB0", 4, 0xFF, -1, 16, 0},
|
||
0x5A: {-1, TLB, "Data TLB0 2-MByte or 4 MByte pages", 2 * 1024, 4, -1, 32, 0},
|
||
0x5B: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 64, 0},
|
||
0x5C: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 128, 0},
|
||
0x5D: {-1, TLB, "Data TLB 4 KByte and 4 MByte pages", 4, -1, -1, 256, 0},
|
||
0x60: {1, DATA_CACHE, "1st-level data cache", 16, 8, 64, -1, 0},
|
||
0x61: {-1, TLB, "Instruction TLB", 4, 0xFF, -1, 48, 0},
|
||
0x63: {-1, TLB, "Data TLB", 1 * 1024 * 1024, 4, -1, 4, 0},
|
||
0x66: {1, DATA_CACHE, "1st-level data cache", 8, 4, 64, -1, 0},
|
||
0x67: {1, DATA_CACHE, "1st-level data cache", 16, 4, 64, -1, 0},
|
||
0x68: {1, DATA_CACHE, "1st-level data cache", 32, 4, 64, -1, 0},
|
||
0x70: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 12, 8, -1, -1, 0},
|
||
0x71: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 16, 8, -1, -1, 0},
|
||
0x72: {1, INSTRUCTION_CACHE, "Trace cache (size in K of uop)", 32, 8, -1, -1, 0},
|
||
0x76: {-1, TLB, "Instruction TLB: 2M/4M pages", 2 * 1024, 0xFF, -1, 8, 0},
|
||
0x78: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 4, 64, -1, 0},
|
||
0x79: {2, DATA_CACHE, "2nd-level cache", 128, 8, 64, -1, 2},
|
||
0x7A: {2, DATA_CACHE, "2nd-level cache", 256, 8, 64, -1, 2},
|
||
0x7B: {2, DATA_CACHE, "2nd-level cache", 512, 8, 64, -1, 2},
|
||
0x7C: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 64, -1, 2},
|
||
0x7D: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 8, 64, -1, 0},
|
||
0x7F: {2, DATA_CACHE, "2nd-level cache", 512, 2, 64, -1, 0},
|
||
0x80: {2, DATA_CACHE, "2nd-level cache", 512, 8, 64, -1, 0},
|
||
0x82: {2, DATA_CACHE, "2nd-level cache", 256, 8, 32, -1, 0},
|
||
0x83: {2, DATA_CACHE, "2nd-level cache", 512, 8, 32, -1, 0},
|
||
0x84: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 32, -1, 0},
|
||
0x85: {2, DATA_CACHE, "2nd-level cache", 2 * 1024, 8, 32, -1, 0},
|
||
0x86: {2, DATA_CACHE, "2nd-level cache", 512, 4, 32, -1, 0},
|
||
0x87: {2, DATA_CACHE, "2nd-level cache", 1 * 1024, 8, 64, -1, 0},
|
||
0xA0: {-1, DTLB, "DTLB", 4, 0xFF, -1, 32, 0},
|
||
0xB0: {-1, TLB, "Instruction TLB", 4, 4, -1, 128, 0},
|
||
0xB1: {-1, TLB, "Instruction TLB 2M pages 4 way 8 entries or" +
|
||
"4M pages 4-way, 4 entries", 2 * 1024, 4, -1, 8, 0},
|
||
0xB2: {-1, TLB, "Instruction TLB", 4, 4, -1, 64, 0},
|
||
0xB3: {-1, TLB, "Data TLB", 4, 4, -1, 128, 0},
|
||
0xB4: {-1, TLB, "Data TLB1", 4, 4, -1, 256, 0},
|
||
0xB5: {-1, TLB, "Instruction TLB", 4, 8, -1, 64, 0},
|
||
0xB6: {-1, TLB, "Instruction TLB", 4, 8, -1, 128, 0},
|
||
0xBA: {-1, TLB, "Data TLB1", 4, 4, -1, 64, 0},
|
||
0xC0: {-1, TLB, "Data TLB: 4 KByte and 4 MByte pages", 4, 4, -1, 8, 0},
|
||
0xC1: {-1, STLB, "Shared 2nd-Level TLB: 4Kbyte and 2Mbyte pages", 4, 8, -1, 1024, 0},
|
||
0xC2: {-1, DTLB, "DTLB 4KByte/2 MByte pages", 4, 4, -1, 16, 0},
|
||
0xC3: {-1, STLB, "Shared 2nd-Level TLB: " +
|
||
"4 KByte /2 MByte pages, 6-way associative, 1536 entries." +
|
||
"Also 1GBbyte pages, 4-way,16 entries.", 4, 6, -1, 1536, 0},
|
||
0xCA: {-1, STLB, "Shared 2nd-Level TLB", 4, 4, -1, 512, 0},
|
||
0xD0: {3, DATA_CACHE, "3nd-level cache", 512, 4, 64, -1, 0},
|
||
0xD1: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 4, 64, -1, 0},
|
||
0xD2: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 4, 64, -1, 0},
|
||
0xD6: {3, DATA_CACHE, "3nd-level cache", 1 * 1024, 8, 64, -1, 0},
|
||
0xD7: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 8, 64, -1, 0},
|
||
0xD8: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 8, 64, -1, 0},
|
||
0xDC: {3, DATA_CACHE, "3nd-level cache", 1 * 1536, 12, 64, -1, 0},
|
||
0xDD: {3, DATA_CACHE, "3nd-level cache", 3 * 1024, 12, 64, -1, 0},
|
||
0xDE: {3, DATA_CACHE, "3nd-level cache", 6 * 1024, 12, 64, -1, 0},
|
||
0xE2: {3, DATA_CACHE, "3nd-level cache", 2 * 1024, 16, 64, -1, 0},
|
||
0xE3: {3, DATA_CACHE, "3nd-level cache", 4 * 1024, 16, 64, -1, 0},
|
||
0xE4: {3, DATA_CACHE, "3nd-level cache", 8 * 1024, 16, 64, -1, 0},
|
||
0xEA: {3, DATA_CACHE, "3nd-level cache", 12 * 1024, 24, 64, -1, 0},
|
||
0xEB: {3, DATA_CACHE, "3nd-level cache", 18 * 1024, 24, 64, -1, 0},
|
||
0xEC: {3, DATA_CACHE, "3nd-level cache", 24 * 1024, 24, 64, -1, 0},
|
||
0xF0: {-1, PREFETCH, "", 64, -1, -1, -1, 0},
|
||
0xF1: {-1, PREFETCH, "", 128, -1, -1, -1, 0},
|
||
0xFF: {-1, NULL, "CPUID leaf 2 does not report cache descriptor " +
|
||
"information, use CPUID leaf 4 to query cache parameters",
|
||
-1, -1, -1, -1, 0},
|
||
}
|
||
|
||
func int32sToBytes(args ...uint32) []byte {
|
||
var result []byte
|
||
|
||
for _, arg := range args {
|
||
result = append(result,
|
||
byte((arg)&0xFF),
|
||
byte((arg>>8)&0xFF),
|
||
byte((arg>>16)&0xFF),
|
||
byte((arg>>24)&0xFF))
|
||
}
|
||
|
||
return result
|
||
}
|